I’m an engineer based in Cambridge, UK.

I have a lot of intrusive thoughts, and engineering is my medium for inflicting them upon the world. This website is an extension of that.

Shower Thoughts

I don’t have a blog, but if I did, this would be it.

• Luke’s Law
• Reversing Bits on Armv6-M
• Testing for Powers of Two
• 16-bit Data Pointers on RV32
• Averaging Pixels as Fast as Possible
• Sparse and Dense Switches on RISC-V
• Simulating Clock Gates

Projects

Hazard3

Hazard3 is an embedded RISC-V core I originally developed for RP2350. It has excellent performance in a small footprint, extensive ISA support, and standard RISC-V debug over JTAG or APB. Development continues on GitHub here.

Read the processor documentation online here.

External Links

GitHub

Twitter

Mastodon

Daily Affirmation

Corrections

This site’s source is here. If you find an error, please file an issue or pull request.